US 12,356,615 B2
Semiconductor device including vertical channel pattern surrounded by protection pattern
Choasub Kim, Hwaseong-si (KR); Dongmin Kyeon, Seongnam-si (KR); Shinyoung Kim, Yongin-si (KR); Hayan Park, Hwaseong-si (KR); Youngsun Cho, Seongnam-si (KR); and Changhyun Hur, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 14, 2022, as Appl. No. 17/693,875.
Claims priority of application No. 10-2021-0076237 (KR), filed on Jun. 11, 2021.
Prior Publication US 2022/0399359 A1, Dec. 15, 2022
Int. Cl. H10B 43/10 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/10 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory cell region on a substrate and comprising a real memory cell region and a dummy memory cell region; and
a connection region extending with the memory cell region in a first direction that is parallel to a surface of the substrate,
wherein the dummy memory cell region comprises a plurality of dummy vertical channel structures spaced apart from each other,
each of the plurality of dummy vertical channel structures comprises a vertical channel pattern in contact with the substrate and penetrating a stack structure comprising a plurality of insulating layers and a plurality of gate electrodes repeatedly stacked in a third direction that is perpendicular to a surface of the substrate, and
a protection pattern surrounds, and is disposed on an outermost side surface of, the vertical channel pattern of at least one of the plurality of dummy vertical channel structures.