US 12,356,613 B2
Semiconductor memory device
Takuya Suzuki, Kuwana (JP); and Ken Iyoda, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 10, 2021, as Appl. No. 17/398,398.
Claims priority of application No. 2021-036035 (JP), filed on Mar. 8, 2021.
Prior Publication US 2022/0285379 A1, Sep. 8, 2022
Int. Cl. H10B 41/27 (2023.01); G11C 8/14 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 8/14 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising
a substrate that includes a first region and a second region arranged in a first direction, wherein
the first region includes:
a plurality of first word line layers stacked in a second direction intersecting with a surface of the substrate;
a first semiconductor layer that extends in the second direction, the first semiconductor layer having an outer peripheral surface opposed to the plurality of first word line layers; and
a first electric charge accumulating film disposed between the plurality of first word line layers and the first semiconductor layer,
the second region includes:
a part of the plurality of first word line layers stacked in the second direction;
a plurality of first insulating layers that are separated from the plurality of first word line layers in a third direction intersecting with the first direction and the second direction, the plurality of first insulating layers being stacked in the second direction;
a first contact that extends in the second direction, the first contact having an outer peripheral surface opposed to the plurality of first insulating layers;
a second semiconductor layer disposed between the plurality of first word line layers and the plurality of first insulating layers, the second semiconductor layer extending in the first direction and the second direction; and
a second electric charge accumulating film disposed between the plurality of first insulating layers and the second semiconductor layer, wherein
a position in the second direction of one of the plurality of first word line layers is assumed to be a first position,
a width in the third direction at the first position of the first semiconductor layer is assumed to be a first width, and
a width in the third direction at the first position of the second semiconductor layer is assumed to be a second width,
the second width is larger than 0.5 times of the first width and smaller than 2.0 times of the first width.