| CPC H10B 20/20 (2023.02) | 20 Claims |
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1. A semiconductor structure, comprising:
a substrate comprising a well region, a first conductivity type doped region in the well region, and a second conductivity type doped region in the well region, wherein the second conductivity type doped region surrounds the first conductivity type doped region and comprises a first portion and a second portion perpendicular to the first portion in a top view;
an anti-fuse disposed in an anti-fuse region of the first conductivity type doped region;
a first transistor and a second transistor disposed in the well region, wherein the anti-fuse is disposed between the first transistor and the second transistor, and the anti-fuse is electrically connected to the first transistor and the second transistor;
a contact structure disposed above the anti-fuse; and
a dielectric layer disposed between the contact structure and the anti-fuse region of the first conductivity type doped region.
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