US 12,356,611 B2
Semiconductor device and method for fabricating the same
Sung Soo Kim, Gyeonggi-do (KR); and Woon Seob Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 12, 2023, as Appl. No. 18/537,244.
Application 18/537,244 is a continuation of application No. 17/403,181, filed on Aug. 16, 2021, granted, now 11,882,694.
Claims priority of application No. 10-2020-0122841 (KR), filed on Sep. 23, 2020.
Prior Publication US 2024/0114681 A1, Apr. 4, 2024
Int. Cl. H10B 12/00 (2023.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01)
CPC H10B 12/50 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 23/535 (2013.01); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming a contact plug that penetrates an inter-layer dielectric layer over a substrate;
forming a capping layer over the inter-layer dielectric layer and the contact plug;
forming a trench that exposes an upper surface of the contact plug by etching the capping layer;
forming a sacrificial layer that fills the trench over the capping layer;
forming a through hole that penetrates the inter-layer dielectric layer, the capping layer, and the sacrificial layer and extends into the substrate;
removing the sacrificial layer to expose the trench;
forming a metal interconnection in the trench; and
forming a through electrode in the through hole.