US 12,356,601 B2
Memory cell design
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 1, 2022, as Appl. No. 17/711,791.
Claims priority of provisional application 63/310,802, filed on Feb. 16, 2022.
Prior Publication US 2023/0262951 A1, Aug. 17, 2023
Int. Cl. G11C 5/06 (2006.01); H10B 10/00 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); G11C 11/412 (2006.01); H10D 89/10 (2025.01)
CPC H10B 10/125 (2023.02) [G11C 5/063 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); G11C 11/412 (2013.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
8. A memory structure, comprising:
a first cell structure comprising:
a first pull-down device (PD-1), a second pull-down device (PD-2), a first pass-gate device (PG-1), and a second pass-gate device (PG-2) disposed in a first p-well on a substrate, and
a first pull-up device (PU-1), a second pull-up device (PU-2), a first isolation device (IS-1), and a second isolation device (IS-2) disposed in an n-well adjacent the first p-well; and
a second cell structure comprising:
a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third pass-gate device (PG-3), and a fourth pass-gate device (PG-4) disposed in a second p-well such that the n-well is sandwiched between the first p-well and the second p-well, and
a third pull-up device (PU-3), a fourth pull-up device (PU-4), a third isolation device (IS-3), and a fourth isolation device (IS-4) disposed in the n-well,
wherein the first isolation device (IS-1) and the third isolation device (IS-3) share a first gate,
wherein the second isolation device (IS-2) and the fourth isolation device (IS-4) share a second gate,
wherein the first gate and the second gate are electrically coupled to a positive supply voltage (CVdd).