US 12,356,600 B2
SRAM memory cell device comprising ferroelectric access and storage transistors
Hung-Li Chiang, Taipei (TW); Jer-Fu Wang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 24, 2022, as Appl. No. 17/703,931.
Prior Publication US 2023/0309285 A1, Sep. 28, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 14/00 (2006.01); H10B 10/00 (2023.01); H10D 30/69 (2025.01)
CPC H10B 10/12 (2023.02) [G11C 11/412 (2013.01); G11C 14/0072 (2013.01); H10D 30/701 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A static random-access memory (SRAM) cell, comprising:
a pair of pull-up transistors, connected to a first reference node;
a pair of pull-down transistors, connected to a second reference node; and
a plurality of access transistors, wherein each of the access transistors comprises:
a substrate;
a source, coupled to a first terminal of one of the pair of pull-up transistors and a second terminal of one of the pair of pull-down transistors;
a drain, coupled to a bit line;
a gate stack structure, disposed over the substrate, coupled to a word line, wherein the gate stack structure comprises:
a gate oxide layer, disposed over the substrate;
a ferroelectric layer, disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and
a first conductive layer, disposed over the ferroelectric layer,
wherein a threshold voltage of the access transistor is changed from a first threshold voltage to a second threshold voltage by biasing to the gate stack structure of the access transistor with a bias voltage greater than an operating voltage of the access transistor, biasing the source or the drain of the access transistor with a ground voltage, and biasing the first reference node and the second reference node with the ground voltage during a pre-program operation,
the access transistor is turned on by biasing the gate stack structure of the access transistor with the operating voltage before and after the pre-program operation,
the threshold voltage of the access transistor is greater than threshold voltages of the pair of pull-up transistors and the threshold voltage of the access transistor is smaller than threshold voltages of the pair of pull-down transistors regardless of logic state stored in the SRAM cell,
the threshold voltage of the access transistor is a minimum voltage between a gate of the access transistor and the source of the access transistor to form a conducting path between the source and the drain of the access transistor, and the threshold voltage of the access transistor is independent from the logic state stored in the SRAM cell.