US 12,356,599 B2
Static random access memory
Chih-Kai Hsu, Tainan (TW); and Chien-Hung Chen, Taipei (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jun. 18, 2020, as Appl. No. 16/905,883.
Claims priority of application No. 202010439957.1 (CN), filed on May 22, 2020.
Prior Publication US 2021/0366913 A1, Nov. 25, 2021
Int. Cl. H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) 11 Claims
OG exemplary drawing
 
1. A static random access memory (SRAM), comprising:
a substrate comprising a first active region and a second active region adjacent to the first active region;
a first gate structure crossing the first active region and the second active region;
a second gate structure adjacent to a first side of the first gate structure and crossing the first active region, wherein the first gate structure and the second gate structure respectively comprise a metal layer and a hard mask layer on the metal layer, and a spacer along sidewalls of the metal layer and the hard mask layer;
a first interlayer dielectric layer on the substrate and surrounding the first gate structure and the second gate structure, wherein the first interlayer dielectric layer has a single layered structure;
a second interlayer dielectric layer on the first interlayer dielectric layer;
an etching stop layer disposed between the first interlayer dielectric layer and the substrate;
a first lower contact structure and a third lower contact structure through the first interlayer dielectric layer and the etching stop layer on the first active region and respectively adjacent to a second side and the first side of the first gate structure, wherein the first lower contact structure and the third lower contact structure respectively comprises a first edge locating between the first active region and the second active region and a second edge opposite to the first edge, wherein the first edges of the first lower contact structure and the third lower contact structure are aligned, the second edges of the first lower contact structure and the third lower contact structure are not aligned, wherein a top surface of the first lower contact structure, a top surface of the first interlayer dielectric layer, top surfaces of the hard mask layer and the spacer of the first gate structure and top surfaces of the hard mask layer and the spacer of the second gate structure are flush with each other; and
a first upper contact structure disposed in the second interlayer dielectric layer on the first lower contact structure and in direct contact with the first lower contact structure and overlapping the second edge of the first lower contact structure, wherein a top surface of the first upper contact structure is flush with a top surface of the second interlayer dielectric layer, a sidewall of the first upper contact structure and the top surface of the first lower contact structure comprise a step profile therebetween.