| CPC H04W 72/21 (2023.01) [H04L 1/0061 (2013.01); H04L 1/0067 (2013.01); H04L 5/0055 (2013.01); H04W 72/23 (2023.01)] | 28 Claims |

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1. An apparatus, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the apparatus to:
receive an uplink grant that schedules a transmission of an uplink shared channel using a first number of symbols that define a nominal repetition, the uplink grant identifying at least a first uplink transmission opportunity and a second uplink transmission opportunity during which the uplink shared channel is to be transmitted, wherein the first uplink transmission opportunity includes a second number of symbols less than the first number of symbols allocated for the uplink shared channel and the second uplink transmission opportunity includes the first number of symbols, the second number of symbols defining the first uplink transmission opportunity as a non-nominal repetition;
multiplex uplink control information (UCI) on the uplink shared channel in the first uplink transmission opportunity based at least in part on the first uplink transmission opportunity including the second number of symbols, wherein the UCI comprises an acknowledgement/negative-acknowledgement (ACK/NACK) feedback;
transmit the uplink shared channel and the UCI comprising the ACK/NACK feedback during the non-nominal repetition in the first uplink transmission opportunity; and
transmit channel state information (CSI) feedback on the uplink shared channel during the nominal repetition and in the second uplink transmission opportunity based at least in part on the second uplink transmission opportunity including the first number of symbols.
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