US 12,355,670 B2
Receiver-based precision congestion control
Rong Pan, Saratoga, CA (US); Pedro Yebenes Segura, San Jose, CA (US); Roberto Penaranda Cebrian, Santa Clara, CA (US); Robert Southworth, Chatsworth, CA (US); Malek Musleh, Portland, OR (US); Jeongkeun Lee, Los Altos, CA (US); and Changhoon Kim, Palo Alto, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 12, 2024, as Appl. No. 18/439,459.
Application 18/439,459 is a continuation of application No. 17/131,672, filed on Dec. 22, 2020, granted, now 12,074,794.
Claims priority of provisional application 63/057,046, filed on Jul. 27, 2020.
Prior Publication US 2024/0195740 A1, Jun. 13, 2024
Int. Cl. H04L 47/129 (2022.01); G06F 15/173 (2006.01); H04L 45/00 (2022.01); H04L 45/74 (2022.01); H04L 47/12 (2022.01); H04L 47/26 (2022.01); H04L 47/267 (2022.01)
CPC H04L 47/129 (2022.05) [G06F 15/17331 (2013.01); H04L 45/38 (2013.01); H04L 45/74 (2013.01); H04L 47/12 (2013.01); H04L 47/26 (2013.01); H04L 47/267 (2022.05)] 40 Claims
OG exemplary drawing
 
1. Integrated circuit for use in association with ternary content-addressable memory (TCAM) in a network switch, the network switch being configurable for use in a network that comprises multiple server nodes and multiple switch nodes, the multiple server nodes comprising at least one server node and at least one other server node, multiple switch nodes comprising at least one switch node and at least one other switch node, the network switch to be comprised in the at least one switch node, the integrated circuit comprising:
packet processing pipeline circuitry configurable to implement ingress and egress pipelines, the ingress and egress pipelines comprising at least one parser stage, multiple match-action stages, and at least one other stage, the at least one parser stage to parse packet header data, the multiple match-action stages to match parsed header field data with at least one portion of table data stored, at least in part, in the TCAM to determine packet processing action data associated with the parsed header field data, the at least one other stage to generate output packet data for output from the integrated circuit; and
traffic manager circuitry to queue ingress pipeline processed packet data for use by at least one egress pipeline;
wherein:
the integrated circuit is to generate telemetry-related information for use in determining packet flow transmit-rate information for at least one packet flow transmitted from the at least one server node in the network;
the packet flow transmit-rate information is to be used by the at least one server node to adjust flow-rate of the at least one packet flow from the at least one server node in the network;
the telemetry-related information is to be accumulated, with other telemetry-related information from the at least one other switch node, to generate accumulated telemetry-related information;
the accumulated telemetry-related information is (1) to be provided to the at least one other server node and (2) for use in generating the packet flow transmit-rate information by the at least one other server node;
the accumulated telemetry-related information comprises:
timestamp information of the at least one switch node and the at least one other switch node;
queue depth information of the at least one switch node and the at least one other switch node; and
bytes transmitted information of the at least one switch node and the at least one other switch node; and
the flow-rate of the at least one packet flow from the at least one server node in the network is to be adjusted, based upon the packet flow transmit-rate information, in association with implementing network congestion control associated with the at least one packet flow.