US 12,355,558 B2
System, apparatus and method for communicating with a variable bit error rate
Howard Heck, Tigard, OR (US); Huimin Chen, Beaverton, OR (US); and Marko Balogh, Stanford, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2021, as Appl. No. 17/482,686.
Prior Publication US 2022/0014304 A1, Jan. 13, 2022
Int. Cl. H04L 1/00 (2006.01)
CPC H04L 1/0009 (2013.01) [H04L 1/0083 (2013.01)] 18 Claims
OG exemplary drawing
 
15. A system comprising:
a first system comprising at least one processor and a first interface circuit, the first interface circuit comprising:
a transaction layer to frame data information from a source circuit into at least one packet;
a link layer coupled to the transaction layer, the link layer to integrity protect the at least one packet; and
a physical layer coupled to the link layer to communicate the at least one packet to a second system, wherein the first interface circuit is to send application-specific data of the at least one packet according to a first bit error rate (BER) and send protocol information of the at least one packet according to a second BER, the first BER greater than the second BER; and
the second system coupled to the first system via a link;
wherein:
the first BER is to be determined based upon acceptable BER indication data that is to be provided by an application that is to consume the application-specific data; and
the acceptable BER indication data is to indicate an acceptable BER that the application is capable of tolerating with respect to communication of application-specific data.