US 12,355,554 B1
Method and apparatus for passing clock signals between time domains
Adi Katz, Ramat Gan (IL); Moran Noiman, Kiryat Ono (IL); Yaakov Yehezkel, Rehovot (IL); and Eliya Babitsky, Caesaria (IL)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jun. 17, 2022, as Appl. No. 17/807,424.
Claims priority of provisional application 63/212,488, filed on Jun. 18, 2021.
Int. Cl. H04J 3/06 (2006.01); H04J 3/16 (2006.01)
CPC H04J 3/0661 (2013.01) [H04J 3/0626 (2013.01); H04J 3/0682 (2013.01); H04J 3/1676 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method of reducing jitter in transmission of a timestamp across a clock domain boundary, the method comprising:
storing N timestamps, generated in N successive clock cycles of an origin clock domain, in N parallel buffers in the origin clock domain under control of a modulo-N counter;
transmitting outputs of the N parallel buffers across the clock domain boundary into a destination clock domain along with the modulo-N counter;
applying an offset to the modulo-N counter in the destination clock domain, that accounts for both uncertainty in the modulo-N counter and instability in the N timestamps, to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffers; and
outputting the selected stable timestamp.