US 12,355,478 B2
Programmable RF front end for wideband ADC-based receiver
Gary A. Ray, Issaquah, IA (US); and Alec Adams, Seattle, WA (US)
Assigned to The Boeing Company, Arlington, VA (US)
Filed by The Boeing Company, Chicago, IL (US)
Filed on Jan. 5, 2022, as Appl. No. 17/568,801.
Claims priority of provisional application 63/142,160, filed on Jan. 27, 2021.
Prior Publication US 2022/0239322 A1, Jul. 28, 2022
Int. Cl. H04B 1/30 (2006.01); H04B 1/00 (2006.01); H04B 1/10 (2006.01)
CPC H04B 1/30 (2013.01) [H04B 1/0078 (2013.01); H04B 1/0096 (2013.01); H04B 1/10 (2013.01); H04B 2001/307 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver comprising:
an antenna block configured to transduce impinging electromagnetic signals into electrical signals;
a signal conditioning block connected and configured to condition electrical signals received from the antenna block;
a down-converter block connected and configured to down-convert conditioned electrical signals received from the signal conditioning block, the down-converter block comprising a plurality of signal channels, wherein each signal channel comprises a respective mixer having an output, a respective switch filter connected to the output of the respective mixer, and a respective down-conversion mixer directly connected to an output of the respective switch filter;
a plurality of programmable frequency synthesizers respectively connected to the mixers the plurality of signal channels of the down-converter block;
a plurality of analog-to-digital converters (ADCs) respectively connected to the plurality of signal channels of the down-converter block; and
a field-programmable gate array (FPGA) connected to the plurality of ADCs, to the plurality of frequency synthesizers, and to the switch filters of the plurality of signal channels of the down-converter block, wherein the FPGA is configured to perform operations comprising:
commanding a frequency search over signals coming into the plurality of ADCs in order to derive interference frequencies of interference signals;
programming the down-converter block by selecting a set of mixer frequencies to be respectively sent to the plurality of frequency synthesizers and a set of bandwidths to be respectively sent to the switch filters, the set of mixer frequencies and the set of bandwidths being designed to remove the interference signals having respective interference frequencies in each signal channel, the selections being calculated to mitigate reductions in dynamic range in the plurality of ADCs due to the interference signals; and
processing digital signals received from the plurality of ADCs after the down-converter block has removed the interference signals.