| CPC H03M 5/145 (2013.01) [H03M 7/40 (2013.01); G06F 7/582 (2013.01)] | 22 Claims |

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1. A transmitter comprising:
a memory configured to store an initial state computed from a bit sequence of an input data packet; and
an arithmetic decoder configured to generate a symbol based on input bits and a symbol frequency table, wherein the symbol frequency table sets frequencies of one or more excluded symbols to 0 and frequencies of one or more allowed symbols to non-zero values,
the transmitter being configured to supply the initial state to the arithmetic decoder as the input bits to iteratively generate a sequence of restricted packets and an ending state, the sequence of restricted packets excluding instances of the one or more excluded symbols, and
the transmitter being configured to transmit the sequence of restricted packets and the ending state on a channel.
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