US 12,355,469 B2
Amplifier circuit to enable accurate measurement of small electrical signals
Artur Wilhelm Suntken, Pretoria (ZA)
Assigned to INSIAVA (PTY) LTD., Pretoria (ZA)
Appl. No. 17/783,194
Filed by INSIAVA (PTY) LTD., Pretoria (ZA)
PCT Filed Nov. 12, 2020, PCT No. PCT/IB2020/060647
§ 371(c)(1), (2) Date Jun. 7, 2022,
PCT Pub. No. WO2021/116796, PCT Pub. Date Jun. 17, 2021.
Claims priority of application No. 2024414 (NL), filed on Dec. 10, 2019.
Prior Publication US 2023/0016043 A1, Jan. 19, 2023
Int. Cl. H03M 3/04 (2006.01); H03F 3/45 (2006.01); H03M 3/00 (2006.01)
CPC H03M 3/484 (2013.01) [H03F 3/45183 (2013.01); H03F 3/45475 (2013.01); H03F 2203/45138 (2013.01); H03F 2203/45631 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An amplifier circuit which includes:
a resistor divider (RREF) comprising n resistive elements (rn) in series where n>1, wherein:
the resistor divider (RREF) comprises two main nodes defined at each end thereof, namely a first main node (a) and a second main node (b);
the resistor divider (RREF) also comprises two readout nodes (d1, d2), namely a first readout node (d1) and a second readout node (d2);
the resistor divider (RREF) comprises resistor nodes (q) defined between adjacent resistive elements;
an input current source (IREF) is connected to the first main node (a);
the resistor divider (RREF) comprises two arrays of addressable switch elements, with a first array of switch elements provided between the respective resistive nodes (q) of the resistor divider (RREF) and the first readout node (d1) and with a second array of switch elements provided between the respective resistive nodes (q) of the resistor divider (RREF) and the second readout node (d2); and
a state of the switch elements is controlled by a feedback signal (sFB) to be open or closed, the readout nodes (d1, d2) thus acting as selectable voltage taps connected to the resistive elements;
a differential pair of transistors (T1, T2) comprising a first transistor (T1) having at least four terminals and a second transistor (T2) having at least four terminals, wherein:
source terminals of each of the transistors (T1, T2) are connected to the second main node (b);
gate terminals of the transistors (T1, T2) are connected to respective input signals (V1, V2);
drain terminals of the transistors (T1, T2) are connected to respective current sources (I1, I2), wherein a differential output signal (VOUT) is created between the drain terminals of the transistors (T1, T2) ; and
bulk terminals of the transistors (T1, T2) are connected to the respective readout nodes (d1, d2), wherein a bulk terminal of the first transistor (T1) is connected to the first readout node (d1) and a bulk terminal of the second transistor (T2) is connected to the second readout node (d2);
wherein the amplifier circuit is configured to perform a function of a difference amplifier in that the transistors (T1, T2) form a differential amplifier with the respective input signals (V1, V2) on their gate terminals; and
wherein the bulk terminals are configured to function as secondary gates in that the bulk terminals affect a threshold of the respective transistors (T1, T2) so as to add or subtract a differential signal derived from the readout nodes (d1, d2) of the resistor divider (RREF) based on voltage signals generated by the operation of the resistor divider (RREF) determined by the feedback signal (SFB).