	US 12,355,464 B2
	Successive approximation register (SAR) digital analog-to-digital converter (ADC), and electronic device
Shuo Fan, Shenzhen (CN); Songrong Bai, Shenzhen (CN); and Jie Wang, Shenzhen (CN)
Assigned to SHENZHEN CVA INNOVATION CO., LTD., Shenzhen (GN)
Appl. No. 18/276,977
Filed by SHENZHEN CVA INNOVATION CO., LTD, Shenzhen (CN)
PCT Filed Apr. 23, 2021, PCT No. PCT/CN2021/089241 § 371(c)(1), (2) Date Aug. 11, 2023, PCT Pub. No. WO2022/174515, PCT Pub. Date Aug. 25, 2022.
Claims priority of application No. 202110190487.4 (CN), filed on Feb. 18, 2021.
Prior Publication US 2024/0120937 A1, Apr. 11, 2024
Int. Cl. H03M 1/46 (2006.01); H03M 1/38 (2006.01); H03M 1/68 (2006.01); H03M 1/76 (2006.01); H03M 1/80 (2006.01)

CPC H03M 1/466 (2013.01) [H03M 1/38 (2013.01); H03M 1/468 (2013.01); H03M 1/68 (2013.01); H03M 1/76 (2013.01); H03M 1/804 (2013.01)]

14 Claims

1. A successive approximation register analog-to-digital converter (SAR ADC), configured to output a n-bit digital signal (D_n−1, D_n−2, . . . , D₁, D₀), n being a positive integer greater than 1, the SAR ADC comprising:

a positive capacitor array comprising (n-m) first capacitors (D_n−2C₁, . . . , D_mC₁, D₀C₁) arranged in parallel, wherein n>m, and m is a positive integer;

a negative capacitor array comprising (n-m) second capacitors (D_n−2C₂, . . . , D_mC₂, D₀C₂) arranged in parallel;

a switch circuit comprising a plurality of groups of first bottom plate switches and a plurality of groups of second bottom plate switches, wherein each group of first bottom plate switches correspond to one first capacitor, each group of second bottom plate switches correspond to one second capacitor, each group of first bottom plate switches are configured to control a bottom plate of a corresponding first capacitor to be connected to a common-mode voltage (V_CM), a positive differential input signal (V_sigp), or one of a plurality of reference voltages, each group of second bottom plate switches are configured to control a bottom plate of a corresponding second capacitor to be connected to a common-mode voltage (V_CM), a negative differential input signal (V_sign), or one of a plurality of reference voltages, and the plurality of reference voltages have offsets with different precisions with respect to the common-mode voltage (V_CM);

a comparator, wherein a positive input terminal of the comparator is connected to a top plate of each first capacitor, a negative input terminal of the comparator is connected to a bottom plate of each second capacitor, and the comparator is configured to sequentially output each bit of digital signal in the n-bit digital signal according to voltages at the positive input terminal and the negative input terminal;

an SAR logic circuit, configured to control the reference voltages to which the plurality of first capacitors are connected through the plurality of groups of first bottom plate switches, and control the reference voltages to which the plurality of second capacitors are connected through the plurality of groups of second bottom plate switches according to each bit of digital signal outputted by the comparator;

wherein the SAR logic circuit is configured to:

according to the most significant bit digital signal (D_n−2) in the n-bit digital signal, connect a bottom plate of each of the first capacitors (D_n−2C₁, . . . , D_mC₁, D₀C₁) to a first initial reference voltage in the plurality of reference voltages, and connect a bottom plate of each of the second capacitors (D_n−2C₂, . . . , D_mC₂, D₀C₂) to a second initial reference voltage in the plurality of reference voltages, wherein the first initial reference voltage and the second initial reference voltage have opposite offset directions with respect to the common-mode voltage, and the offset amounts of the first initial reference voltage and the second initial reference voltage with respect to the common-mode voltage are not the maximum offset in offset amounts of the plurality of reference voltages with respect to the common-mode voltage, and are also not the minimum offset;

control a target reference voltage connected to a bottom plate of the k-th bit first capacitor (D_kC₁) according to the k-th bit digital signal (D_k) and the most significant bit digital signal (D_n−1) in the n-bit digital signal, and control a target reference voltage connected to a bottom plate of the k-th bit second capacitor (D_kC₂) according to the k-th bit digital signal (D_k) and the most significant bit digital signal (D_n−1), wherein k=n−2, . . . , m;

control a target reference voltage to which a bottom plate of the least significant bit first capacitor (D₀C₁) is connected according to the most significant bit digital signal (D_n−1) and each bit of digital signal of a low m-bit digital signal (D_m−1, . . . , D₀) in the n-bit digital signal, and control a target reference voltage to which a bottom plate of the least significant bit second capacitor (D₀C₂) is connected according to the most significant bit digital signal (D_n−1) and each bit of digital signal of the low m-bit digital signal (D_m−1, . . . , D₀) in the n-bit digital signal.