US 12,355,461 B2
System and method for calibrating weighting errors in split capacitance successive approximation analog-to-digital converters
Hua Fan, Chengdu (CN); Yilin Liu, Chengdu (CN); Wei Zhang, Chengdu (CN); Jing Luo, Chengdu (CN); Panfeng Zhao, Chengdu (CN); and Quanyuan Feng, Chengdu (CN)
Assigned to UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, Chengdu (CN)
Filed by Univ. Electronic Science and Technology of China, Chengdu (CN)
Filed on Sep. 22, 2023, as Appl. No. 18/472,717.
Claims priority of application No. 202310968524.9 (CN), filed on Aug. 2, 2023.
Prior Publication US 2025/0047291 A1, Feb. 6, 2025
Int. Cl. H03M 1/60 (2006.01); H03M 1/10 (2006.01); H03M 1/40 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/1033 (2013.01) [H03M 1/406 (2013.01); H03M 1/462 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system for calibrating weighting errors in an analog-to-digital converter (ADC), comprising:
a comparator, a P-terminal array, a N-terminal array and a control logic unit;
wherein the comparator has a positive input terminal and a negative input terminal switchably connectable to a common mode reference voltage;
the positive input of the comparator is connected to the P-terminal array;
the P-terminal array comprises a least significant bit (LSB) array having L bits, a bridge capacitor CBR, and a most significant bit (MSB) array having M bits;
the negative input of the comparator is connected to the N-terminal array;
the MSB array contains 2M−1 unit capacitances, wherein a first capacitor corresponding to the unit capacitances has a first plate connected directly to the comparator, each remaining capacitor corresponding to the unit capacitances has a first plate switchably connected to the comparator, and each of the capacitors corresponding to the unit capacitances has a lower plate with a common connection that is switchably connected to a positive reference voltage, a negative reference voltage, or a differential positive input voltage;
the LSB array contains 2L unit capacitors, wherein each of the unit capacitors has an upper plate connected to the comparator and a lower plate switchably connected to the positive reference voltage, the negative reference voltage, or the differential positive input voltage;
the bridge capacitor is between a common connection point of the upper plates of the LSB array unit capacitors and an upper plate common connection point of the capacitors corresponding to the unit capacitances in the MSB array;
the system further comprises a calibration digital-to-analog converter (DAC) array connected to the upper plates of the LSB array unit capacitors, wherein the calibration DAC array comprises a binary array of P-bit unit capacitors, a calibration structure, and a ground switch group, and the calibration structure includes (i) a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor connected in series and (ii) a first switch and a second switch configured to generate a plurality of capacitance values from the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and
the control logic unit outputs the positive reference voltage, the negative reference voltage, or the differential positive input voltage.