US 12,355,452 B2
Fast-locking all-digital phase-locked loop and applications thereof
Carsten Wulff, Trondheim (NO); Tor Øyvind Vedal, Trondheim (NO); Ola Bruset, Trondheim (NO); Shankkar Balasubramanian, Trondheim (NO); Ruben Undheim, Trondheim (NO); and Harald Garvik, Trondheim (NO)
Assigned to Nordic Semiconductor ASA, Trondheim (NO)
Appl. No. 18/569,459
Filed by NORDIC SEMICONDUCTOR ASA, Trondheim (NO)
PCT Filed Jun. 13, 2022, PCT No. PCT/EP2022/065967
§ 371(c)(1), (2) Date Dec. 12, 2023,
PCT Pub. No. WO2022/263348, PCT Pub. Date Dec. 22, 2022.
Claims priority of application No. 20215694 (FI), filed on Jun. 14, 2021.
Prior Publication US 2024/0283459 A1, Aug. 22, 2024
Int. Cl. H03L 7/10 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/104 (2013.01) [H03L 7/093 (2013.01); H03L 7/099 (2013.01); H03L 2207/50 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An all-digital phase-locked loop, ADPLL, for a radio receiver, radio transmitter or radio transceiver, the ADPLL comprising:
a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal;
a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal being either a transmission signal of the radio transmitter or transceiver or a local oscillator signal of the radio receiver or transceiver, wherein the SC-DCO comprises a variable load comprising a set of one or more parallel switchable capacitor banks and the radio frequency signal is used as the feedback signal;
a phase-locked loop controller operatively connected between the time-to-digital converter and the SC-DCO for controlling the SC-DCO based on the digital time signal received from the time-to-digital converter for achieving a phase and frequency lock; and
digital processing means communicatively connected to the phase-locked loop controller for:
maintaining, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal; and
causing the phase-locked loop controller to adjust a switching configuration of the SC-DCO for generating a radio frequency signal having a frequency of the plurality of frequencies according to the lookup table for expediting locking of the all-digital phase-locked loop.