US 12,355,449 B2
Phase interpolator circuit, reception circuit, and semiconductor integrated circuit
Hideki Kano, Kanagawa (JP)
Assigned to SOCIONEXT INC., Yokohama (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Jul. 13, 2023, as Appl. No. 18/351,902.
Application 18/351,902 is a continuation of application No. PCT/JP2021/003969, filed on Feb. 3, 2021.
Prior Publication US 2023/0361763 A1, Nov. 9, 2023
Int. Cl. H03K 5/13 (2014.01); H03K 17/687 (2006.01)
CPC H03K 5/13 (2013.01) [H03K 17/6871 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A phase interpolator circuit configured to generate an output clock signal having a phase according to a phase interpolation code based on a first input clock signal and a second input clock signal having a first phase difference therebetween, the phase interpolator circuit comprising:
a first generation circuit configured to generate a first intermediate current based on the first input clock signal according to the phase interpolation code;
a second generation circuit configured to generate a second intermediate current based on the second input clock signal according to the phase interpolation code;
a synthesis circuit configured to synthesize the first intermediate current and the second intermediate current to generate the output clock signal; and
a correction circuit configured to correct a current amount of at least one of the first intermediate current and the second intermediate current based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value, wherein:
the first generation circuit includes a first transistor configured to operate as a current source, a first gate voltage according to the phase interpolation code being supplied to a gate of the first transistor,
the second generation circuit includes a second transistor configured to operate as a current source, a second gate voltage according to the phase interpolation code being supplied to a gate of the second transistor, and
the correction circuit includes a third transistor configured to operate as a current source, a third gate voltage according to the correction code being supplied to a gate of the third transistor.