US 12,355,445 B2
Techniques for duty cycle correction
Christopher P. Mozak, Portland, OR (US); Ralph S. Li, Portland, OR (US); Chin Wah Lim, Bayan Lepas (MY); Mahmoud Elassal, King City, OR (US); Anant Balakrishnan, Hillsboro, OR (US); and Isaac Ali, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 8, 2023, as Appl. No. 18/534,430.
Application 18/534,430 is a continuation of application No. 16/716,234, filed on Dec. 16, 2019, granted, now 11,916,554.
Prior Publication US 2024/0113700 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/00 (2006.01); G06F 11/16 (2006.01); H03K 3/017 (2006.01); H03K 5/135 (2006.01); H03K 5/156 (2006.01); H03L 7/081 (2006.01); H03K 5/15 (2006.01)
CPC H03K 3/017 (2013.01) [G06F 11/1679 (2013.01); H03K 5/135 (2013.01); H03K 5/1565 (2013.01); H03L 7/0816 (2013.01); H03K 5/15 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
duty cycle correction circuitry to:
measure a duty cycle generated by a target clock via use of a sample clock, the duty cycle to be measured based on a periodic sampling of the target clock that samples the target clock at a rate that is greater than 1 prime number ratio of a reference clock cycle time, wherein the reference clock cycle time is to set a measurement cycle time over which the duty cycle is to be measured;
determine a duty cycle error based on the periodic sampling of the target clock during the measurement cycle time; and
adjust the duty cycle generated by the target clock based, at least in part, on the duty cycle error.