US 12,355,440 B2
Slew rate controlled output buffer circuit and semiconductor device
Ryota Terauchi, Hsinchu (TW); and Chia-Jung Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 2, 2023, as Appl. No. 18/346,264.
Prior Publication US 2025/0007518 A1, Jan. 2, 2025
Int. Cl. H03K 19/0185 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 19/00361 (2013.01); H03K 19/00384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a process monitor circuit, configured to measure process information of the semiconductor device;
a controller, electrically connected to the process monitor circuit, and configured to generate a trimming code based on the measured process information; and
an output buffer, electrically connected to the controller, and configured to adjust a first bias current and a second bias current based on the trimming code,
wherein the output buffer comprises: a first output driver transistor, a second output driver transistor, a first feedback capacitance, and a second feedback capacitance, wherein the first feedback capacitance is coupled between a gate and a first terminal of the first output driver transistor, and the second feedback capacitance is coupled between a gate and a first terminal of the second output driver transistor.