US 12,355,439 B2
Reset independent glitch filter
Amod Phadke, Bangalore (IN); Vinay Kumar Garipelli, Bangalore (IN); Naveen Kumar Narala, Bengaluru (IN); Manjunath Kachenahalli Rangegowda, Bangalore (IN); and Ravi Shankar Srinivasan, Chennai (IN)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 26, 2023, as Appl. No. 18/324,785.
Prior Publication US 2024/0396551 A1, Nov. 28, 2024
Int. Cl. H03K 19/003 (2006.01); H03K 19/096 (2006.01); H03K 19/20 (2006.01)
CPC H03K 19/00361 (2013.01) [H03K 19/096 (2013.01); H03K 19/20 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A glitch filtering circuit, comprising:
a counting circuit configured to provide one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time;
a flipflop clocked by a clock signal and configured to provide an output of the glitch filtering circuit;
a threshold detect circuit configured to generate a select signal based on the one or more counter output signals; and
a multiplexer configured to provide a multiplexed signal to an input of the flipflop, the multiplexed signal having a signaling state that is selected in accordance with the select signal.