US 12,355,434 B1
Integrated circuit control apparatus and method
Muhammad Ahmed, Garland, TX (US); Wenchao Qu, Plano, TX (US); and Kuangyu Chiang, Saint Paul, TX (US)
Assigned to Halo Microelectronics International, Campbell, CA (US)
Filed by Halo Microelectronics International, Campbell, CA (US)
Filed on Jan. 9, 2024, as Appl. No. 18/408,516.
Int. Cl. H03K 17/00 (2006.01); H03K 17/56 (2006.01)
CPC H03K 17/56 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an enable circuit having a first input configured to receive a serial data in (SDI) signal, a second input configured to receive a not chip select (nCS) signal, a third input configured to receive a hold (HLD) signal, and an output configured to generate an internal enable signal for controlling a power-up process and a power-down process of an integrated circuit; and
a digital core circuit configured to generate the HLD signal after the integrated circuit is powered up by the SDI signal and the nCS signal.