US 12,355,433 B2
Power on reset (POR) circuit
Sapna Sharma, Bangalore (IN); Sanjay Kumar Wadhwa, Noida (IN); and Neha Goel, Noida (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on May 3, 2023, as Appl. No. 18/311,696.
Claims priority of application No. 202341015473 (IN), filed on Mar. 8, 2023.
Prior Publication US 2024/0305289 A1, Sep. 12, 2024
Int. Cl. H03K 17/22 (2006.01); H03K 3/037 (2006.01); H03K 17/284 (2006.01)
CPC H03K 17/223 (2013.01) [H03K 3/0377 (2013.01); H03K 17/284 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A power on reset (POR) circuit, comprising:
an input configured to receive a power supply voltage;
an output configured to be coupled to a set of logic circuits;
a hysteresis device having a first terminal coupled to the output;
a delay circuit configured to output a first signal to the set of logic circuits prior to a delay time;
wherein the delay circuit is configured to output a second signal to the set of logic circuits after the delay time;
wherein the delay circuit includes,
a capacitance device,
a voltage drop device having a first terminal coupled to the input and configured to receive the power supply voltage, and
a MOSFET having a drain terminal configured to be coupled to both a second terminal of the hysteresis device and a first terminal of the capacitance device;
wherein the MOSFET has an on-resistance and includes a source terminal coupled to a second terminal of the voltage drop device,
wherein the MOSFET includes a gate coupled to a ground reference; and
wherein the capacitance device has a capacitance and a second terminal coupled to the ground reference;
wherein a second terminal of the hysteresis device is coupled to the output; and
wherein the on-resistance of the MOSFET and the capacitance of the capacitance device together are configured to set the delay time.