US 12,355,355 B2
Switching power converter circuit and conversion control circuit and method thereof
Hung-Yu Cheng, Taipei (TW); Wan-Hsuan Yang, Hsinchu (TW); and Chi-Hsun Wu, New Taipei (TW)
Assigned to RICHTEK TECHNOLOGY CORPORATION, Zhubei (TW)
Filed by Richtek Technology Corporation, Zhubei (TW)
Filed on Aug. 22, 2023, as Appl. No. 18/453,586.
Claims priority of application No. 111135536 (TW), filed on Sep. 20, 2022.
Prior Publication US 2024/0097567 A1, Mar. 21, 2024
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 1/088 (2006.01); H03K 7/08 (2006.01)
CPC H02M 3/158 (2013.01) [H02M 1/0025 (2021.05); H02M 1/088 (2013.01); H03K 7/08 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A conversion control circuit configured to control a power stage circuit, wherein the power stage circuit comprises a power switch, a switching device and an inductor which are coupled to one another, the power switch and the switching device are configured to switch the inductor to convert an input power to generate an output power, wherein the conversion control circuit comprises:
an error amplification circuit, configured to generate an error amplified signal according to a feedback signal relevant to the output power and a reference signal;
a ramp signal generating circuit, configured to generate a ramp signal; and
a pulse width modulation (PWM) circuit, configured to generate a PWM signal according to the error amplified signal and the ramp signal, wherein the power switch is switched according to the PWM signal;
the PWM circuit comprising:
a modulation comparison circuit, configured to compare the error amplified signal and the ramp signal to generate a modulation comparison signal;
an adjustable oscillation circuit, configured to generate a clock signal according to the modulation comparison signal, wherein the clock signal is adjustable and has a preset cycle period; and
a logic circuit, configured to generate the PWM signal according to the modulation comparison signal and the clock signal;
wherein the PWM circuit generates the PWM signal according to following steps:
S1: triggering the clock signal to generate a first changing edge;
S2: enabling the PWM signal at the first changing edge to control the power switch to be turned on;
S3: when an on-time after the PWM signal is enabled exceeds a preset minimum on-time, and when the modulation comparison signal indicates that an electrical characteristic of the output power reaches an output level, disabling the PWM signal to control the power switch to be turned off; and
S4: when an off-time after the PWM signal is disabled exceeds a preset minimum off-time, and when the modulation comparison signal indicates that the electrical characteristic of the output power does not reach the output level, and when a present cycle period of the clock signal has reached the preset cycle period, returning to repeat the step S1.