| CPC H02J 7/0063 (2013.01) [H01M 10/0525 (2013.01); H01M 10/425 (2013.01); H01M 10/46 (2013.01); H02J 7/00032 (2020.01); H02J 7/0047 (2013.01); H02J 7/00712 (2020.01)] | 18 Claims |

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1. An apparatus comprising a memory configured to communicate with one or more processors, the memory having instructions stored thereon that, in response to execution by the one or more processors, cause the one or more processors to perform operations that cause an energy storage device that provides a direct current to power an alternating current (AC) load, the operations comprising:
receiving, by the one or more processors, sensor data from each of one or more sensors;
commanding, by the one or more processors, an electrical switch to transition between an open state and a closed state, wherein:
a duty cycle for an operational cycle of the electrical switch is between 80% and 98%, and
a frequency of the operational cycle is between 90 Hz and 135 Hz; and
in response to the periodically transitioning the electrical switch, generating a rectangular wave form from the energy storage device that supplies the direct current, the rectangular wave form supplied to a bus of a power source.
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