US 12,355,026 B2
Method of writing to or erasing multi-bit memory storage device
Meng-Han Lin, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); Martin Liu, Hsinchu (TW); Sai-Hooi Yeong, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 24, 2023, as Appl. No. 18/518,716.
Application 18/518,716 is a division of application No. 17/871,315, filed on Jul. 22, 2022, granted, now 11,848,381, issued on Dec. 19, 2023.
Application 17/871,315 is a division of application No. 17/185,549, filed on Feb. 25, 2021, granted, now 11,532,746, issued on Dec. 20, 2022.
Claims priority of provisional application 63/032,082, filed on May 29, 2020.
Prior Publication US 2024/0097032 A1, Mar. 21, 2024
Int. Cl. G11C 11/22 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/30 (2023.01)
CPC H01L 29/78391 (2014.09) [G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 29/6684 (2013.01); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal, the method comprising:
setting the second bit to a logical 1 value, the setting a second bit including:
applying a gate voltage to the gate terminal; and
applying a first source/drain voltage to the second S/D terminal; and
wherein the first source/drain voltage is lower than the gate voltage.