CPC H01L 25/50 (2013.01) [H01L 21/76898 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/83047 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1425 (2013.01)] | 20 Claims |
1. A method comprising:
bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die through solder bonding or micro bump bonding to form a die stack, wherein the III-V die comprises:
a (111) semiconductor substrate; and
a first circuit comprising:
a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate, and wherein the CMOS die comprises:
a (100) semiconductor substrate;
a second circuit comprising:
an n-type transistor on the (100) semiconductor substrate; and
a p-type transistor on the (100) semiconductor substrate, wherein the first circuit is electrically connected to the second circuit;
dispensing an underfill into a gap between the III-V die and the CMOS die;
forming a through-via in the III-V die;
polishing the (111) semiconductor substrate to reveal the through-via; and
attaching a heat sink to the III-V die through a thermal interface material, wherein the thermal interface material physically contacts the through-via.
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