US 12,355,020 B2
Display device having boost capacitor
Jin Sung An, Seongnam-si (KR); Seok Je Seong, Seongnam-si (KR); Ji Seon Lee, Hwaseong-si (KR); and Se Wan Son, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Aug. 30, 2023, as Appl. No. 18/458,526.
Application 18/458,526 is a continuation of application No. 17/935,372, filed on Sep. 26, 2022, granted, now 11,776,466.
Application 17/935,372 is a continuation of application No. 17/187,996, filed on Mar. 1, 2021, granted, now 11,455,943, issued on Sep. 27, 2022.
Claims priority of application No. 10-2020-0027043 (KR), filed on Mar. 4, 2020.
Prior Publication US 2023/0419886 A1, Dec. 28, 2023
Int. Cl. G09G 3/32 (2016.01); H01L 25/16 (2023.01); H10H 20/817 (2025.01); H10H 20/857 (2025.01); H10K 59/131 (2023.01)
CPC H01L 25/167 (2013.01) [G09G 3/32 (2013.01); H10H 20/817 (2025.01); H10H 20/857 (2025.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display device, comprising:
a first transistor including a polycrystalline semiconductor layer;
a second transistor including a polycrystalline semiconductor layer and connected to the first transistor;
a third transistor including an oxide semiconductor layer and connected to the first transistor;
a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor, wherein the fourth transistor is connected to a gate electrode of the first transistor;
a boost capacitor including a first electrode and a second electrode overlapping the first electrode, wherein the first electrode is connected to the second transistor, and the second electrode is connected to at least one of the third transistor and the fourth transistor;
a light emitting diode including an anode, a cathode, and a light emitting layer;
a seventh transistor connected to the light emitting diode;
a first initialization voltage line connected to an electrode of the fourth transistor and transmitting a first initialization voltage; and
a second initialization voltage line connected to an electrode of the seventh transistor and transmitting a second initialization voltage different from the first initialization voltage, wherein the first initialization voltage line and the second initialization voltage line are disposed on different layers from each other.