US 12,355,015 B2
Semiconductor device
Tomohiro Iguchi, Himeji Hyogo (JP); and Makoto Mizukami, Ibo Hyogo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Feb. 25, 2022, as Appl. No. 17/681,453.
Claims priority of application No. 2021-152688 (JP), filed on Sep. 17, 2021.
Prior Publication US 2023/0092229 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1304 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an insulating substrate;
a first metal layer on a surface of the insulating substrate, the first metal layer having a first connection region at which the first metal layer is electrically connected to a first main terminal;
a second metal layer on the surface of the insulating substrate, the second metal layer having a second connection region at which the second metal layer is electrically connected to a second main terminal;
a third metal layer on the surface of the insulating substrate between the first metal layer and the second metal layer, the third metal layer having a third connection region at which the third metal layer is electrically connected to an output terminal;
a plurality of first semiconductor chips aligned along a first direction on the first metal layer, each first semiconductor chip including a first upper electrode, a first lower electrode, a first gate electrode, a first silicon carbide layer, and a first Schottky barrier diode;
a plurality of second semiconductor chips aligned along the first direction on the third metal layer, each second semiconductor chip including a second upper electrode, a second lower electrode, a second gate electrode, a second silicon carbide layer, and a second Schottky barrier diode;
a first connection wire electrically connecting a first upper electrode of a first semiconductor chip to the third metal layer; and
a second connection wire electrically connecting a second upper electrode of a second semiconductor chip to the second metal layer, wherein
the second semiconductor chips are between the first semiconductor chips and the third metal layer in a second direction perpendicular to the first direction,
the first connection region and the second connection region are spaced from each other along a third direction intersecting the second direction,
the third connection region is between the first and second connection regions in the third direction,
the angle between the third direction and the first direction is between 20° and 0°, range end points inclusive, and
the angle between an extension direction of the second connection wire and the second direction is between 20° and 0°, range end points inclusive.