US 12,355,008 B2
Methods of fabricating package structure
Ming-Fa Chen, Taichung (TW); Chao-Wen Shih, Hsinchu County (TW); Min-Chien Hsiao, Taichung (TW); Nien-Fang Wu, Chiayi (TW); Sung-Feng Yeh, Taipei (TW); and Tzuan-Horng Liu, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 13, 2024, as Appl. No. 18/662,916.
Application 18/662,916 is a division of application No. 17/676,239, filed on Feb. 21, 2022, granted, now 12,015,013.
Application 17/676,239 is a continuation of application No. 16/886,698, filed on May 28, 2020, granted, now 11,264,362, issued on Mar. 1, 2022.
Prior Publication US 2024/0297151 A1, Sep. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H01L 21/304 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/3043 (2013.01); H01L 21/78 (2013.01); H01L 23/3157 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 24/94 (2013.01); H01L 2224/80001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
bonding a first semiconductor die to a surface of a semiconductor wafer, and the semiconductor wafer comprising at least one second semiconductor die;
forming first grooves on the surface of the semiconductor wafer;
forming an insulating encapsulation over the surface of the semiconductor wafer to laterally encapsulate the first semiconductor die and fill the first grooves to form a reconstructed wafer;
forming a redistribution circuit structure on the reconstructed wafer, wherein the redistribution circuit structure is spaced apart from the insulating encapsulation by the semiconductor wafer; and
performing a wafer sawing process to saw the reconstructed wafer along scribe lines aligned with the first grooves, wherein a maximum lateral dimension of the first grooves is wider than a maximum cutting width of the wafer sawing process.