US 12,355,005 B2
Semiconductor package and method of fabricating the same
Jongho Park, Cheonan-si (KR); Un-Byoung Kang, Hwaseong-si (KR); Sechul Park, Bucheon-si (KR); Hyojin Yun, Suwon-si (KR); Ju-Il Choi, Seongnam-si (KR); and Atsushi Fujisaki, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 22, 2022, as Appl. No. 17/700,879.
Claims priority of application No. 10-2021-0105292 (KR), filed on Aug. 10, 2021.
Prior Publication US 2023/0046782 A1, Feb. 16, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/02057 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06582 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate that includes a plurality of vias;
a first chip stack on the substrate, the first chip stack including a plurality of first semiconductor chips that are sequentially stacked on the substrate; and
a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips,
wherein each of the first non-conductive layers comprises first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips,
wherein the more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips,
wherein the first extension of the first non-conductive layer between the substrate and the lowermost one of the first semiconductor chips is on the first lateral surface of the lowermost one of the first semiconductor chips,
wherein the first extension of the first non-conductive layer between the two lowermost ones of the first semiconductor chips is on the first lateral surfaces of each of the two lowermost ones of the first semiconductor chips, and
wherein the first extension of the first non-conductive layer between the substrate and the lowermost one of the first semiconductor chips and the first extension of the first non-conductive layer between the two lowermost ones of the first semiconductor chips are vertically spaced apart from each other without being in contact with each other.
 
13. A semiconductor package, comprising:
a substrate that includes a plurality of vias;
a first semiconductor chip mounted on a first chip terminal on the substrate;
a first non-conductive layer that fills a space between the substrate and the first semiconductor chip;
a second semiconductor chip mounted on a second chip terminal on a top surface of the first semiconductor chip;
a second non-conductive layer that fills a space between the first semiconductor chip and the second semiconductor chip;
a third semiconductor chip mounted on a third chip terminal on a top surface of the second semiconductor chip;
a third non-conductive layer that fills a space between the second semiconductor chip and the third semiconductor chip; and
a molding layer on the substrate, the molding layer surrounding the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip,
wherein a first width of the first non-conductive layer between the substrate and the first semiconductor chip is greater than a second width of the second non-conductive layer between the first semiconductor chip and the second semiconductor chip,
wherein the first non-conductive layer and the second non-conductive layer include the same material,
wherein a first rigidity of the first non-conductive layer is greater than a second rigidity of the second non-conductive layer,
wherein the first non-conductive layer comprises a first extension that protrudes outwardly from and is on a first side surface of the first semiconductor chip,
wherein the second non-conductive layer comprises a second extension that protrudes outwardly from a second side surface of the second semiconductor chip and is on the first side surface of the first semiconductor chip and the second side surface of the second semiconductor chip,
wherein the first and second extensions are vertically spaced apart from each other without being in contact with each other, and
wherein a first thickness of the first non-conductive layer between the substrate and the first semiconductor chip is smaller than a second thickness of the second non-conductive layer between the first semiconductor chip and the second semiconductor chip.
 
15. A semiconductor package, comprising:
a substrate that includes a plurality of vias;
a first semiconductor chip on a first chip terminal on the substrate;
a first non-conductive layer in a space between the substrate and the first semiconductor chip;
a second semiconductor chip on a second chip terminal on a top surface of the first semiconductor chip;
a second non-conductive layer in a space between the first semiconductor chip and the second semiconductor chip;
a third semiconductor chip on a third chip terminal on a top surface of the second semiconductor chip; and
a third non-conductive layer in a space between the second semiconductor chip and the third semiconductor chip,
wherein a first width of the first non-conductive layer between the substrate and the first semiconductor chip is greater than a second width of the second non-conductive layer between the first semiconductor chip and the second semiconductor chip,
wherein the first non-conductive layer comprises a first extension that protrudes outwardly from and is on a first side surface of the first semiconductor chip,
wherein the second non-conductive layer comprises a second extension that protrudes outwardly from a second side surface of the second semiconductor chip and is on the first side surface of the first semiconductor chip and the second side surface of the second semiconductor chip,
wherein the first and second extensions are vertically spaced apart from each other without being in contact with each other, and
wherein a first thickness of the first non-conductive layer between the substrate and the first semiconductor chip is smaller than a second thickness of the second non-conductive layer between the first semiconductor chip and the second semiconductor chip.