US 12,355,003 B2
Semiconductor devices and data storage systems including the same
Seungyoon Kim, Seoul (KR); Junghoon Jun, Hwaseong-si (KR); Sanghun Chun, Suwon-si (KR); and Jeehoon Han, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 24, 2022, as Appl. No. 17/582,387.
Claims priority of application No. 10-2021-0050100 (KR), filed on Apr. 16, 2021.
Prior Publication US 2022/0336421 A1, Oct. 20, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 24/05 (2013.01); H01L 25/18 (2013.01); H01L 24/08 (2013.01); H01L 2224/05007 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05011 (2013.01); H01L 2224/05016 (2013.01); H01L 2224/05078 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05138 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05681 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/08146 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/01014 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first structure including a substrate, circuit devices on the substrate, first pad layers on the circuit devices, and a second pad layer on the circuit devices; and
a second structure on the first structure,
wherein the second structure comprises,
first conductive layer including first openings on corresponding ones of the first pad layers, respectively, and a second opening on the second pad layer, the first conductive layer having a first region and a second region,
a stack structure including gate electrodes spaced apart from each other on the first region and the second region, the gate electrodes stacked on the first conductive layer in a vertical direction and extending in a first direction perpendicular to the vertical direction,
channel structures penetrating through the stack structure on the first region, each of the channel structures including a channel layer,
separation regions penetrating through the stack structure on the first region and the second region and extending in the first direction,
gate contact plugs penetrating through the stack structure, the gate contact plugs connected to the gate electrodes, respectively, and the gate contact plugs connected to the first pad layers through the first openings of the first conductive layer, respectively,
a source connection conductive layer being in contact with a lower surface of the first conductive layer, and the source connection conductive layer having a hole between the second opening of the first conductive layer and the second pad layer,
a source contact plug spaced apart from the stack structure, the source contact plug extending into the hole of the source connection conductive layer through the second opening of the first conductive layer, and the source contact plug connected to the second pad layer and the source connection conductive layer, and
a through-insulating layer in the second opening of the first conductive layer and surrounding a side surface of the source contact plug while extending partially into the hole of the source connection conductive layer.