	US 12,355,002 B2
	Hyperchip
Mark T. Bohr, Aloha, OR (US); Wilfred Gomes, Portland, OR (US); Rajesh Kumar, Portland, OR (US); Pooya Tadayon, Portland, OR (US); and Doug Ingerly, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 25, 2024, as Appl. No. 18/615,654.
Application 18/615,654 is a division of application No. 18/128,958, filed on Mar. 30, 2023, granted, now 11,984,430.
Application 18/128,958 is a continuation of application No. 17/226,967, filed on Apr. 9, 2021, granted, now 11,824,041, issued on Nov. 21, 2023.
Application 17/226,967 is a continuation of application No. 16/348,448, granted, now 11,024,601, issued on Jun. 1, 2021, previously published as PCT/US2017/068049, filed on Dec. 21, 2017.
Claims priority of provisional application 62/440,275, filed on Dec. 29, 2016.
Prior Publication US 2024/0243099 A1, Jul. 18, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01)

CPC H01L 25/0655 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5384 (2013.01); H01L 24/13 (2013.01); H01L 2225/06541 (2013.01)]

20 Claims

1. An integrated circuit assembly, comprising:

a first integrated circuit chip comprising:

a bulk silicon substrate;

transistor devices on the bulk silicon substrate;

a first group of interconnect levels on the transistor devices;

a second group of interconnect levels on the first group of interconnect levels; and

through silicon vias in the bulk silicon substrate and in the first group of interconnect levels but not in the second group of interconnect levels, wherein the second group of interconnect levels covers the through silicon vias; and

a second integrated circuit chip mounted on the first integrated circuit chip, the second integrated circuit chip having an area smaller than and within an area of the first integrated circuit chip, and the second integrated circuit chip electrically coupled to the through silicon vias of the first integrated circuit chip.