US 12,354,997 B2
Package structure and manufacturing method thereof
Sheng-Hsiang Chiu, Tainan (TW); Chia-Min Lin, Hsinchu (TW); Tzu-Ting Chou, Hsinchu (TW); Sheng-Feng Weng, Taichung (TW); Chao-wei Li, Hsinchu (TW); Chih-Wei Lin, Hsinchu County (TW); and Ching-Hua Hsieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/462,005.
Prior Publication US 2023/0062468 A1, Mar. 2, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 21/56 (2013.01); H01L 23/3135 (2013.01); H01L 23/3185 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a substrate, wherein the substrate is a circuit substrate having a core layer and plated through holes passing through the core layer;
a first semiconductor element, disposed on the substrate;
a second semiconductor element, disposed on the substrate, wherein the second semiconductor element and the first semiconductor element perform different functions; and
a molding layer, disposed over the substrate and covering at least a top surface of the substrate,
wherein the molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element, a top surface of the molding layer is higher than a top surface of the first semiconductor element, and the molding layer has a first opening and a second opening extending from the top surface of the molding layer to the top surface of the first semiconductor element and a rib portion located on the top surface of the first semiconductor element and between the first and second openings, the top surface of the first semiconductor element is a non-active surface and exposed by the first and second openings.