US 12,354,992 B2
First layer interconnect first on carrier approach for EMIB patch
Changhua Liu, Chandler, AZ (US); Xiaoying Guo, Phoenix, AZ (US); Aleksandar Aleksov, Chandler, AZ (US); Steve S. Cho, Chandler, AZ (US); Leonel Arana, Phoenix, AZ (US); Robert May, Chandler, AZ (US); and Gang Duan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/958,296.
Application 17/958,296 is a continuation of application No. 17/366,469, filed on Jul. 2, 2021.
Application 17/366,469 is a continuation of application No. 16/646,084, granted, now 11,088,103, issued on Aug. 10, 2021, previously published as PCT/US2018/013620, filed on Jan. 12, 2018.
Prior Publication US 2023/0027030 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/20 (2013.01) [H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/214 (2013.01); H01L 2224/215 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first bridge die having a top, a bottom, a first side between the top and bottom, and a second side between the top and bottom, the second side opposite the first side, the first bridge die having a vertical thickness between the top and bottom, and the first bridge die having a plurality of through vias;
a second bridge die laterally spaced apart from the first bridge die, the second bridge die having a top, a bottom, a first side between the top and bottom, and a second side between the top and bottom, the second side opposite the first side, the second bridge die having a vertical thickness between the top and bottom, and the second bridge die having a plurality of through vias;
a core material laterally adjacent to and in contact with the first side and the second side of the first bridge die, the core material on and vertically overlapping with a portion of the top of the first bridge die, the core material laterally adjacent to and in contact with the first side and the second side of the second bridge die, and the core material on and vertically overlapping with a portion of the top of the second bridge die;
a first conductive pillar laterally adjacent to the first side of the first bridge die, wherein the first conductive pillar extends through the core material;
a second conductive pillar laterally adjacent to the second side of the first bridge die, wherein the second conductive pillar extends through the core material;
a build-up layer over the core material, the build-up layer over the first bridge die, over the second bridge die, over the first conductive pillar, and over the second conductive pillar, and the build-up layer having an uppermost surface;
a first die over a first portion of the build-up layer, the first die coupled to the first bridge die and to the first conductive pillar by the first portion of the build-up layer, and the first die having a bottommost surface above the uppermost surface of the build-up layer, wherein the first bridge die is partially within a footprint of the first die; and
a second die over a second portion of the build-up layer, the second die coupled to the first bridge die and to the second conductive pillar by the second portion of the build-up layer, and the second die having a bottommost surface above the uppermost surface of the build-up layer, wherein the first bridge die is partially within a footprint of the second die, and the second bridge die is coupled to the second die and is partially within the footprint of the second die.