US 12,354,982 B2
Memory devices with backside bond pads under a memory array
Eric N. Lee, San Jose, CA (US); and Akira Goda, Tokyo (JP)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Mar. 15, 2024, as Appl. No. 18/607,339.
Application 18/607,339 is a continuation of application No. 17/854,428, filed on Jun. 30, 2022, granted, now 11,935,853.
Application 17/854,428 is a continuation of application No. 16/940,040, filed on Jul. 27, 2020, granted, now 11,410,949, issued on Aug. 9, 2022.
Prior Publication US 2024/0312933 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/48 (2006.01); H01L 25/18 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H01L 24/05 (2013.01) [H01L 21/4814 (2013.01); H01L 23/481 (2013.01); H01L 24/03 (2013.01); H01L 25/18 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2224/05025 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1438 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a memory die, the method comprising:
forming control circuitry on a frontside of a substrate that has the frontside and a backside;
forming a memory array over the control circuitry, wherein the memory array is electrically coupled with the control circuitry, and wherein the control circuitry is between the memory array and the frontside of the substrate;
forming, after forming the control circuitry and the memory array, a through-silicon via (TSV) through the substrate; and
forming a bond pad on the backside of the substrate, wherein the bond pad is electrically coupled with the control circuitry via the TSV, and wherein the bond pad is configured for coupling the memory array to one or more external components.