US 12,354,978 B2
Coupled loop and void structure integrated in a redistribution layer of a chip package
Po-Wei Chiu, Hsinchu (TW); Tzu-No Chen, Kaohsiung (TW); Hong Shi, Los Gatos, CA (US); Li-Sheng Weng, San Diego, CA (US); and Young Soo Lee, Santa Clara, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Apr. 19, 2022, as Appl. No. 17/724,063.
Prior Publication US 2023/0335510 A1, Oct. 19, 2023
Int. Cl. H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/645 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package comprising:
an integrated circuit (IC) die;
a package substrate having a die side and a ball side; and
a redistribution layer (RDL) disposed between the IC die and the die side of the package substrate, the RDL comprising a plurality of conductive layers patterned to form RDL circuitry within the RDL, the RDL circuitry connecting the IC die to the package substrate; wherein the plurality of conductive layers forming the RDL circuitry further comprise:
a first metal layer having a first contact pad coupled to a first trace, the first trace arranged in a first coil, a first end of the first coil coupled to the first contact pad; and
a second metal layer having a second trace, the second trace arranged in a second coil, a first end of the second coil coupled to a second end of the first coil by a first via, wherein an opening is formed in the second metal layer that at least partially surrounds the second coil.