US 12,354,977 B2
Memory device
Ayako Kawanishi, Yokkaichi (JP); and Shinya Arai, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 25, 2022, as Appl. No. 17/822,248.
Claims priority of application No. 2022-048021 (JP), filed on Mar. 24, 2022.
Prior Publication US 2023/0307387 A1, Sep. 28, 2023
Int. Cl. H01L 23/60 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/60 (2013.01) [H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/30205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising
a first chip and a second chip that are in contact with each other on a first surface divided into a first region, a second region surrounding the first region, and a third region surrounding the second region, wherein
the first chip includes:
a substrate including a first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type different from the first conductivity type;
a first electrode unit including a continuous conductor surrounding the first region in the second region; and
a second electrode unit surrounding the first region while being spaced from the first electrode unit in the second region,
the second chip includes:
a first interconnect layer;
a third electrode unit including a continuous conductor surrounding the first region in the second region and being in contact with the first electrode unit;
a fourth electrode unit surrounding the first region while being spaced from the third electrode unit in the second region and being in contact with the second electrode unit;
a first wall unit being in contact with the first interconnect layer, including a continuous conductor surrounding the first region, and being electrically coupled to the first diffusion region via the third electrode unit and the first electrode unit; and
a second wall unit being in contact with the first interconnect layer, surrounding the first region while being spaced from the first wall unit, and being electrically coupled to the second diffusion region via the fourth electrode unit and the second electrode unit, and
each of a first ratio of an area covered by the first electrode unit and the second electrode unit to the second region, and a second ratio of an area covered by the third electrode unit and the fourth electrode unit to the second region is equal to or more than 3% and is equal to or less than 40%.