US 12,354,976 B2
Semiconductor device and electronic device
Ikue Mitsuhashi, Kanagawa (JP); and Toshiaki Iwafuchi, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Sep. 15, 2023, as Appl. No. 18/368,882.
Application 18/368,882 is a continuation of application No. 17/297,247, granted, now 11,869,853, previously published as PCT/JP2019/047234, filed on Dec. 3, 2019.
Claims priority of application No. 2018-227498 (JP), filed on Dec. 4, 2018.
Prior Publication US 2024/0006349 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 31/00 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H10F 39/00 (2025.01)
CPC H01L 23/585 (2013.01) [H01L 23/562 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H10F 39/809 (2025.01); H01L 2224/05647 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/0616 (2013.01); H01L 2224/06517 (2013.01); H01L 2224/08145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first substrate;
a second substrate; and
at least one guard structure including a first guard element, a second guard element, and a third guard element,
wherein the first substrate and the second substrate are bonded to one another at a bonding interface between a first surface of the first substrate and a second surface of the second substrate,
wherein the first guard element is in the first substrate and spaced apart from the third guard element by a portion of the first substrate,
wherein the second guard element is in the second substrate and spaced apart from the third guard element by a portion of the second substrate,
wherein the third guard element includes portions in the first surface and the second surface to bond the first substrate to the second substrate, and
wherein the at least one guard structure surrounds a power source pad.