US 12,354,975 B2
Guard ring structure
Min-Feng Ku, Hsinchu (TW); Yao-Chun Chuang, Hsinchu (TW); Cheng-Chien Li, Hsinchu (TW); and Ching-Pin Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 11, 2022, as Appl. No. 17/693,027.
Claims priority of provisional application 63/282,227, filed on Nov. 23, 2021.
Prior Publication US 2023/0163084 A1, May 25, 2023
Int. Cl. H01L 23/58 (2006.01); H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 21/76832 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a substrate;
an interconnect structure over the substrate;
a guard ring structure disposed in the interconnect structure;
a via structure vertically extending through the guard ring structure; and
a top metal feature disposed directly over and in contact with the guard ring structure and the via structure,
wherein the guard ring structure comprises a plurality of guard ring layers,
wherein each of the plurality of guard ring layers comprises a lower portion and an upper portion disposed over the lower portion,
wherein sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.
 
9. An integrated circuit (IC) structure, comprising:
a substrate;
an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of etch stop layers,
a plurality of intermetal dielectric (IMD) layers interleaving the plurality of etch stop layers, and
a plurality of guard ring layers stacked one over another to form a guard ring structure, each of the plurality of guard ring layers being disposed within one of the plurality of etch stop layers and one of the plurality of IMD layers immediately overlying the one of the plurality of etch stop layers;
a via structure vertically extending through a center of the guard ring structure; and
a top metal feature disposed directly over and in contact with a top surface of the guard ring structure and a top surface of the via structure.
 
17. A semiconductor structure, comprising:
a substrate;
an interconnect structure over the substrate;
a guard ring structure disposed in and extending through the interconnect structure;
a via structure vertically extending through a center of the guard ring structure and into the substrate such that the via structure is surrounded by the guard ring structure; and
a top metal feature disposed directly over and in contact with top surfaces of the guard ring structure and the via structure,
wherein the guard ring structure comprises a smooth inner surface.