| CPC H01L 23/562 (2013.01) [H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |

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1. A semiconductor device comprising a semiconductor chip including a substrate, a first surface of the substrate, and a side surface rising from an edge of the first surface, wherein
the semiconductor chip further includes:
a memory cell array including a plurality of first insulating layers and a plurality of first conducting layers stacked alternately in a normal direction of the first surface;
a first stacked body provided at an outer peripheral end portion of the semiconductor chip when viewed from the normal direction and including a plurality of first layers and a plurality of second layers alternately stacked in the normal direction;
a first resin that overlaps at least a portion of the first stacked body, when viewed from the normal direction;
a second resin separated from the first resin and located closer to the center side of the semiconductor chip than the first resin, when viewed from the normal direction;
a first structure body provided in at least a part between the first resin and the second resin when viewed from the normal direction and extending from a position higher than the first stacked body to a position lower than the first stacked body; and
a first control circuit that is provided below the memory cell array and that overlaps at least a portion of the memory cell array when viewed from the normal direction.
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