US 12,354,969 B2
Semiconductor device and method of manufacture
Jiun Yi Wu, Zhongli (TW); Chen-Hua Yu, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); and Chien-Hsun Lee, Chu-tung Town (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 28, 2023, as Appl. No. 18/520,958.
Application 17/107,181 is a division of application No. 16/185,861, filed on Nov. 9, 2018, granted, now 10,854,552, issued on Dec. 1, 2020.
Application 18/520,958 is a continuation of application No. 17/107,181, filed on Nov. 30, 2020, granted, now 11,854,988.
Claims priority of provisional application 62/692,166, filed on Jun. 29, 2018.
Prior Publication US 2024/0096812 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/02 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
encapsulating a plurality of interconnect structures in a first encapsulant, wherein each interconnect structure of the plurality of interconnect structures comprises a through-substrate via (TSV) extending through a first substrate of the interconnect structure;
bonding a first semiconductor die to a first side of each of the plurality of interconnect structures using a plurality of first external contacts;
encapsulating each of the first semiconductor dies in a second encapsulant; and
bonding a plurality of second external contacts to a second side of each of the plurality of interconnect structures.