US 12,354,966 B2
Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
Mou-Shiung Lin, Hsinchu (TW); and Jin-Yuan Lee, Hsinchu (TW)
Assigned to iCometrue Company Ltd., Hsinchu County (TW)
Filed by iCometrue Company Ltd., Zhubei (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/228,787.
Application 18/228,787 is a continuation of application No. 17/535,989, filed on Nov. 27, 2021, granted, now 11,749,610.
Application 17/535,989 is a continuation of application No. 16/686,107, filed on Nov. 16, 2019, granted, now 11,211,334, issued on Dec. 18, 2021.
Claims priority of provisional application 62/891,386, filed on Aug. 25, 2019.
Claims priority of provisional application 62/882,941, filed on Aug. 5, 2019.
Claims priority of provisional application 62/768,978, filed on Nov. 18, 2018.
Prior Publication US 2023/0378074 A1, Nov. 23, 2023
Int. Cl. H01L 23/52 (2006.01); G11C 5/06 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H03K 19/094 (2006.01)
CPC H01L 23/5384 (2013.01) [G11C 5/06 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H03K 19/094 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A multi-chip package comprising:
a first semiconductor integrated-circuit (IC) chip comprising a first silicon substrate, a plurality of first transistors at a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate and coupling to the plurality of first transistors;
a second semiconductor integrated-circuit (IC) chip over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip comprises a second silicon substrate, a plurality of second transistors at a bottom surface of the second silicon substrate and a second interconnection scheme under the second silicon substrate and coupling to the plurality of second transistors, wherein the second interconnection scheme comprises a first silicon-oxide-containing layer and a first bonding pad each at a bottom of the second semiconductor integrated-circuit (IC) chip, wherein the first bonding pad is in an opening in the first silicon-oxide-containing layer and couples to the first semiconductor integrated-circuit (IC) chip, wherein the first bonding pad comprises a first copper layer in the opening in the first silicon-oxide-containing layer and a first adhesion metal layer having a first portion at a sidewall of the first copper layer and a second portion at a top of the first copper layer, wherein the first copper layer has a bottom surface coplanar with a bottom surface of the first silicon-oxide-containing layer, wherein the second semiconductor integrated-circuit (IC) chip has a first edge over the first semiconductor integrated-circuit (IC) chip and a second edge opposite to the first edge and over the first semiconductor integrated-circuit (IC) chip;
a sealing layer over the first semiconductor integrated-circuit (IC) chip and at a same horizontal level as the second semiconductor integrated-circuit (IC) chip;
a first metal via over the first semiconductor integrated-circuit (IC) chip and vertically in the sealing layer;
a second metal via over the first semiconductor integrated-circuit (IC) chip, vertically in the sealing layer and coupling to the first bonding pad of the second semiconductor integrated-circuit (IC) chip;
a first metal pad vertically over and coupling to the first metal via;
a polymer layer over the second semiconductor integrated-circuit (IC) chip and sealing layer, wherein an opening in the polymer layer is vertically over the first metal pad and first metal via; and
a first metal bump on the first metal pad, vertically over the first metal via and at a top of the multi-chip package, wherein the first metal bump couples to the first metal via through the first metal pad.