US 12,354,958 B2
Semiconductor devices and methods of formation
Shu-Cheng Chin, Hsinchu (TW); Chih-Chien Chi, Hsinchu (TW); Hsin-Ying Peng, Hsinchu (TW); Jau-Jiun Huang, Kaohsiung (TW); Ya-Lien Lee, Baoshan Township (TW); Kuan-Chia Chen, Hsinchu (TW); Chia-Pang Kuo, Taoyuan (TW); and Yao-Min Liu, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 18, 2022, as Appl. No. 17/655,510.
Prior Publication US 2023/0299002 A1, Sep. 21, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/76844 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76865 (2013.01); H01L 23/5226 (2013.01)] 21 Claims
OG exemplary drawing
 
13. A method, comprising:
forming an opening through one or more first dielectric layers and over a first conductive structure that is included in a second dielectric layer;
forming a graphene barrier layer on sidewalls of the opening;
performing a surface treatment of the graphene barrier layer to create nucleation sites in the graphene barrier layer;
forming, using the nucleation sites, one or more metal liner layers over the graphene barrier layer;
forming a second conductive structure in the opening over the first conductive structure and over the one or more metal liner layers; and
forming a cobalt capping layer over the second conductive structure.