| CPC H01L 23/5283 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |

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1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a first three-dimensional memory array located in a first memory array region; and
a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region, wherein the electrically conductive layers comprise common word lines for the first three-dimensional memory array and for the second three-dimensional memory array,
wherein:
the alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing;
the electrically conductive layers continuously extend between the first memory array region and a second memory array region and comprise a respective bridge region that is located in the inter-array region;
the bridge region of the at least one of the electrically conductive layers has a variable width along the second horizontal direction;
the inter-array region comprises a stepped surface region comprising vertically-extending surface segments of the alternating stack that are perpendicular to the first horizontal direction;
the stepped surface region further comprises horizontally-extending surface segments connecting a respective neighboring pair of vertically-extending surface segments of the vertically-extending surface segments; and
the horizontally-extending surface segments have a variable lateral extent along the second horizontal direction including at least one stepwise increase as a function of a lateral distance from the first memory array region toward the second memory array region.
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