| CPC H01L 23/5283 (2013.01) [H01L 21/0259 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/53242 (2013.01); H01L 23/535 (2013.01); H10D 30/031 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01)] | 20 Claims |

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1. A semiconductor device, comprising:
a substrate;
a stack of channel layers disposed over the substrate and extending lengthwise along a first direction;
a source feature and a drain feature disposed over the substrate, wherein the stack of channel layers extend between the source feature and the drain feature;
a gate structure disposed over the substrate and extending along a second direction perpendicular to the first direction, wherein the gate structure is disposed between the source feature and the drain feature and the gate structure has a gate stack that engages the stack of channel layers;
a gate via disposed directly on the gate stack;
a source via connected to the source feature; and
a drain via connected to the drain feature, wherein:
the source via has a first dimension along the second direction and a second dimension along the first direction,
the drain via has a third dimension along the second direction and a fourth dimension along the first direction,
a ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension,
the gate via has a fifth dimension along the second direction and a sixth dimension along the first direction,
the fifth dimension is less than the third dimension and the sixth dimension is less than the fourth dimension,
the ratio of the first dimension to the second dimension is greater than a ratio of the fifth dimension to the sixth dimension, and
the gate stack has a gate stack width along the first direction, wherein the gate stack width is greater than the sixth dimension.
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