US 12,354,947 B2
Multilayer-type on-chip inductor structure
Sheng-Yuan Lee, New Taipei (TW)
Assigned to VIA LABS, INC., New Taipei (TW)
Filed by VIA LABS, INC., New Taipei (TW)
Filed on Jun. 9, 2021, as Appl. No. 17/342,699.
Claims priority of application No. 110103222 (TW), filed on Jan. 28, 2021.
Prior Publication US 2022/0238436 A1, Jul. 28, 2022
Int. Cl. H10D 1/20 (2025.01); H01F 27/28 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5227 (2013.01) [H01F 27/2804 (2013.01); H01L 23/5226 (2013.01); H10D 1/20 (2025.01); H01F 2027/2809 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multilayer-type on-chip inductor structure, comprising:
an insulating redistribution layer disposed on an inter-metal dielectric layer; and
first and second winding portions symmetrically arranged in the inter-metal dielectric layer and the insulating redistribution layer with respect to a symmetrical axis, the first and second winding portions each comprising at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity, and first and second semi-circular stacking layers each comprising:
a first trace layer disposed in the insulating redistribution layer; and
a second trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first trace layer, wherein a first slit opening is formed in and passes through the second trace layer and extends along a length of the second trace layer,
wherein there is an equal number of trace layers in the first semi-circular stacking layer as in the second semi-circular stacking layer.