| CPC H01L 23/5226 (2013.01) [H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 19 Claims |

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1. A memory device comprising:
a substrate including a memory region, and an external region of the memory region;
a first conductor layer arranged in the memory region apart from the substrate in a first direction crossing a plane parallel to the substrate;
a second conductor layer arranged in the external region apart from the first conductor layer in a second direction in the plane;
a third conductor layer arranged in the external region apart from the second conductor layer on an opposite side of the first conductor layer with respect to the second conductor layer in the second direction;
a first member including in the external region, a first lower portion extending in the first direction between the first conductor layer and the second conductor layer and reaching a lower side of the first conductor layer and the second conductor layer, and a first upper portion including a side surface outside an extension of a side surface of the first lower portion on an upper side of the first lower portion;
a second member including in the external region, a second lower portion extending in the first direction between the second conductor layer and the third conductor layer and reaching a lower side of the second conductor layer and the third conductor layer, and a second upper portion including a side surface outside an extension of a side surface of the second lower portion on an upper side of the second lower portion, the second member being arranged apart from the first member in the second direction; and
a first insulating member including in the external region, a lower end located on a lower side of the first upper portion and the second upper portion, and an upper end located on an upper side of the first upper portion and the second upper portion, and extending in the first direction between the first upper portion and the second upper portion.
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