| CPC H01L 23/49838 (2013.01) [H01L 23/49822 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 23/481 (2013.01); H01L 24/09 (2013.01); H01L 24/13 (2013.01); H01L 24/80 (2013.01); H01L 24/81 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08148 (2013.01); H01L 2224/0913 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/81203 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01)] | 15 Claims |

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1. A chip package structure, comprising:
a chipset, wherein the chipset comprises a plurality of chips distributed horizontally;
a first Re-Distribution Layer (RDL) disposed on a first surface of the chipset; and
a bonding pad region, wherein the bonding pad region comprises a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL; wherein all bonding pads corresponding to the plurality of chips are centrally disposed in the bonding pad region;
wherein a horizontal area of the bonding pad region is less than or equal to a total horizontal area of the first surface of the chipset;
the horizontal area of the bonding pad region is less than or equal to a horizontal area of any one of the plurality of chips, and
an orthographic projection of the bonding pad region on the first surface is within an orthographic projection of one of the plurality of chips on the first surface.
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