| CPC H01L 23/49838 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H01L 25/162 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73104 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] | 20 Claims |

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1. A device, comprising:
a semiconductor chip; and
a redistribution layer structure connected to the semiconductor chip, the redistribution layer structure including:
a first region including:
a first bump connected to the semiconductor chip;
a second bump; and
a plurality of first redistribution layers connected between the first bump and the second bump;
a second region laterally surrounding the first region, the second region including a plurality of second redistribution layers; and
an isolation region laterally separating the plurality of first redistribution layers from the plurality of second redistribution layers, wherein the isolation region includes at least one region that is straight, continuous, extends from an upper surface of the redistribution layer structure to a lower surface of the redistribution layer structure, and has at least a selected width,
wherein the isolation region includes a plurality of first support structures positioned between the plurality of first redistribution layers and the plurality of second redistribution layers.
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